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Magma takes on mixed-signal SoCs

Targeting consumer applications, SoCs (Systems on Chips) have integrated more and more analog circuitry in recent years. The circuits in question have been not merely the unavoidable PLLs and high-speed I/Os, but also control loops and precision signal paths spanning both audio and video. This situation has forced SoC designers into the world of mixed-signal design. To date, there have been two main approaches: One is to outsource the analog-block designs, import them again as hard IP (intellectual property), and hope that they work. The other approach is to use tool suites, such as Cadence’s (www.cadence.com) Virtuoso, targeting skilled analog designers but integrating digital fl ows. This approach allows analog experts on the SoC team to do a custom analog design in the same database their digital colleagues are using for the rest of the SoC design, somewhat easing integration and verification.

Magma Design Automation recently introduced another alternative—one that is in keeping with the company’s guiding concept that modest designs shouldn’t require immodest expertise or license fees. The Titan platform will provide an environment in which not-full-custom analog design can proceed in parallel with digital design, merging during the physical-design back-end and working from a unifi ed database. According to Ashutosh Mauskar, Magma’s vice president of product and business development, Titan provides two paths by which a team can create analog designs. One is a schematic editor, from which the circuit description binds to foundry-device models to create a simulatable netlist. The other is an IP-oriented scheme, in which Magma defi nes commonly used analog functions in a topology template and a set of constraint equations. “The circuits will come right out of a textbook on analog design,” Mauskar says, “so they will be familiar and useful.”

The template-and-equation format allows Titan’s processmigration tool to explore a range of alternative implementations in a new process technology within the constraints, offering designers a choice of migrated circuit designs. Thus, migrating an analog function in the Magma library to a new process node—although not exactly pushbutton—will be heavily automated. Working with the schematic and template tools, Titan will offer an analog-simulation environment that Magma based on the FineSim analogplacement tool. At this point, the isolation of the analog and digital designs ends, and both the simulated and placed analog netlist and the digital Talus netlist fl ow into a merged tool suite. That suite begins with a layout editor and a shapebased router that understands analog-circuit constraints, such as shielding styles and linelength control, preserving the operating characteristics of at least conservatively drawn analog circuits through the routing process.

The final stage in the flow is one of extraction, timing, and checking stage. For this step, Magma has incorporated its full-chip digital-timing tools: LVS (layout-versus-schematic) checking, DRC (designrule- checking), and extraction. Although these concepts are familiar for digital designs, performing a full-chip LVS or extraction for an SoC with analog blocks is a different matter. LVS checking for analog circuits, for instance, requires rules decks from both the user and their foundry, according to Mauskar. Extracting analog components and model parameters from shapes is an unsolved problem, so the tools need this additional data. And extraction, which can use simple approximations for digital-timing purposes, also becomes far more complex in the analog domain. Magma employs a new transistor- level extraction tool based on the company’s QuickCap capacitance extractor. Again, analog extraction is a work in progress, and future developments should use the detailed extraction algorithms that cell designers use.

All of the data for both the analog and digital nets goes into a unifi ed database that complies with Open Access, reducing the version-control problems that can plague mixed-signal SoCs when the analog and digital designs proceed in isolation. The Titan approach addresses a number of these problems with mixedsignal SoC fl ows, but it is not a panacea, a universal custom design tool, or a substitute for having skilled analog designers, Mauskar warns. The template- based approach to analog- circuit design is more than adequate for normal, moderate- performance circuits, but it does not push a process node to its physical limits or implement science projects. It is for moderate-performance functional blocks. The migration tool also does not intervene in a circuit topology to fi nd a better approach for a sigmadelta converter at 65 nm, for example. “The tools should work well with any technology node you can characterize accurately,” Mauskar says. “But there is no way to replace human intelligence on the most demanding requirements. That’s not what we are trying to do.”

Magma is phasing the rollout of Titan over the course of the year. This quarter will see the release of the Titan schematic capture, mixed-signallayout and -routing, and chipfi nishing tools. Magma will release the rest of the fl ow, including the analog-circuit templates and migration tool and the mixed-signal fl oorplanning tool, in beta form this quarter, and in production versions in the third quarter of this year.

Magma Design Automation, www.magma-da.com