Micron’s architecture change to extend the life of NAND

EDN Europe, 14 Dec 2010

Micron Technology recently introduced a high-density NAND flash memory range under the name ClearNAND, and the company has now added clarification on how it intends the product to fit into the market. ClearNAND packages will contain up to eight NAND dice plus a controller chip, but the architecture differs slightly from earlier product; in the new product, the integrated controller performs error-correction (ECC) and other low-level tasks the Micron generically classes as “error management”: higher-level memory management tasks such as block management, wear-leveling and command management are the province of a separate controller chip. Up until the present generation of flash chips, Micron says, it made sense to combine all of the ECC and other management functions in a single controller. However, going forward to 20-nm processes and beyond, ECC demands more and more logic – 24-bit ECC routines are already in use. ECC, and other low-level memory management functions become very dependent on, and specific to, the particular process technology that builds the NAND chips, making it appropriate to place that functionality close to the memory dice themselves. Higher-level functions such as block management are more closely related to the external application and it makes sense to place them in a separate package, Micron believes; that chip will continue to interface to the NAND memory package via the ONFI (Open NAND Flash Interface) bus.
In a separate category, for applications such as cellular handsets where designers want “black-box” NAND functionality and don’t want to mange the memory at all, Micron will continue to provide eMMC (embedded MultiMedia Card) solutions with MMC interface, flash memory and multi-function controller in a signal package. But many users fall into the category of having to manage the memory (that is, using what Micron terms “raw” NAND chips), while as the company’s Kevin Kilbuck, Director of Strategic Marketing, puts it, “they can’t keep up with the [ever-more complex] ECC – future error-management requirements could exceed 1million gates of logic per NAND channel.” For those designers, Micron offers ClearNAND, relieving them of the ECC problem while leaving them free to shape application-dependent memory-management functions. Kilbuck says that future silicon process shrinks will yield generations of chips that will demand this approach. Micron will, he says, develop “toolbox” of error management techniques and IP that it will use throughout its controller-based memory product ranges.
Micron will offer two variants of ClearNAND, that it will build with its 25-nm multi-level cell process; the standard feature set, on packages hosting 8-32 Gbytes, will be for simple replacement of “raw” NAND; with an asynchronous interface it will support up to 50 Mtransfers/sec and 4-way command queuing. Enhanced-command-set devices, at 16-64 Gbytes, will have asynchronous or synchronous interfacing at up to 200 MT/sec and 16-way command queuing. Standard and Enhanced devices will occupy standard-pin-out LGA or BGA packages, for what Kilbuck terms a “modest” price premium over conventional chips, and are available now.