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Mixed-signal-IC designers get help with nanometre processes

Building on an initial launch in the North- American market, EDA start-up Solido is now introducing its tools to the European chip-design community. Solido makes tools for the transistorlevel designer, working with analogue and mixed-signal designs to analyse and circumvent the effects of process variations in advanced silicon technologies. There is a growing problem, Solido asserts, as designers move from 130 nm through technologies with geometries as small as 32 or even, in the future, 22 nm. Along that transition, designers progressively see their results impacted by statistical variations, by well-proximity effects as structures simply get closer together as geometries shrink, channel-stress effects—greater amounts of germanium in transistor channels, that process designers add to increase carrier mobility, stress the crystal structure—and a mysterious “new effect” at 22 nm. Conventionally, Solido says, IC designers either accept a lower performance than the process is actually capable of, or they accept a loss of yield because they cannot predict the spread in performance that results from the impact of all of these new factors, when their chip goes to manufacturing. Solido aims its tools at mixedsignal designers, optimising chip blocks in the size range of hundreds of transistors. Not only can its tools analyse these effects, the company claims, but it can explore the sensitivity of yield variation to specific variables—in other words, it can guide you to make the detail design changes that will have the biggest impact on the loss of yield that your chip will suffer.

This area of EDA has become a “hot topic”: Synopsys recently added Custom Designer to its Galaxy chip-design offering. The tool set—which, Synopsys says, is the “fi rst modern-era mixed-signal design solution”— integrates simulation, analysis, parasitic extraction and physical verifi cation for the benefi t of the custom designer. By the custom designer, Synopsys means the engineer laying out and optimising analogue circuitry and the parts of digital circuit blocks that have analogue dependencies. The company openly admits that its objective is to provide those designers with a tool flow that avoids the need for them to leave the Synopsys environment and invoke tools from other vendors —mainly Cadence—to complete this part of their project. The tool set has all the look-andfeel of the Virtuoso environment— although it is, Synopsys emphasises, a “clean-room” and completely new software build—to avoid any loss of productivity with a tool transition. Designers can also exchange data between digital and analogue domains in the fl oorplanning, placement, routing and chip-editing phases of a project, without loss of detail. All Synopsys simulators are accessible, and results from parasitic extraction become available—dynamically—within Custom Designer.

Solido, www.solido.com. Synopsys, www.synopsys.com.