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Motor-drive MCU has twin inverter outputs

Renesas designed the SH7137F microcontroller family to meet the needs of designers working in industrial inverters and motor drives in the range of 1 to 100 kW. The chip has 256 kbytes of Renesas’ MONOS flash memory on board. Speaking recently to EDN Europe, Terukazu Watanabe, chief engineer at the company’s MCU Business Unit, identified its flash technology (metal-oxide-nitrideoxide- silicon) as a key differentiator in the microcontroller market. MONOS, Watanabe says, provides very high reliability and fast access time—at as little as 10 nsec, it allows devices to run directly from flash memory, removing any need for a cache. This brings an added advantage of power savings. The technology also scales well, Renesas says, with a small cell size.

The µC’s MONOS—12.5- nsec speed in the current generation—supports fully deterministic 80-MHz zero-wait operation with over 100 Dhrystone MIPS CPU performance. It has two timer units, each capable of driving a motor—with protection features to shut-down in the presence of dangerous conditions— and two 12-bit fast ADCs for measuring the phase currents; it thus provides for three sample-andhold circuits in each ADC. The conversion time is as fast as 1.25 µsec. For deeply embedded real-time systems, the devices has fast, vectored interrupts; Renesas based it on the SH2 core with 16 general- purpose registers, each 32-bit wide, and a MAC (multiply- accumulate unit) for DSP algorithms. There is a varied suite of peripherals and I/O ports, plus up to 57 generalpurpose I/O lines; the chips come in 80- and 100-pin QFP packages. An automotive version— the SH7147F—supports 125°C operation, for drives that are built near to or even into the motor.

Dual-core architecture for embedded

At the same time, Renesas has introduced the fi rst of what will comprise a family of dual-core processors for high-performance embedded systems. It designed the SH7786 group, with twin SH- 4A cores, for high-performance multimedia systems, especially car information systems. The chip delivers up to 1920 MIPS when operating at 533 MHz. The device will sample to selected customers in October 2008 and will be available for general industrial markets in 2009. It will support both symmetric and asymmetric multiprocessing; the processor group will have features to communicate and ensure interoperability between operating systems in separate domains, while preventing them interfering with each others’ operation. Developers will thus, Renesas says, be able to use software resources originally intended for single-processor systems to build multicore distributed systems in a short time. In the 7786, the clock frequencies for each CPU, and their low-power modes, can be set independently, to minimise power consumption while responding to changes in processing load. Over time, Renesas says it intends to expand the concept to include four-core processors and dual-core SoC designs with features for specifi c systems such as car navigation and image processing.

Renesas, www.renesas.com.