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EDN Europe's Editor Graham Prophet posts a selection of comments and insights prompted by the many items of industry news and rumour that cross the editorial desk or are gathered on his frequent travels to interviews, press conferences and events around Europe - and further afield - and somehow never find their way to the magazine or the web site, recovering some of the information otherwise lost in the noise level...

Friday, March 07, 2008

Need to know

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From Embedded World last week, to DATE next week. Increasingly, I don’t understand events like DATE. At least, I don’t understand the (significant) part of it that is concerned with design of leading-edge, SoC digital designs. There is the proverbial elephant in the room on this one. Or, rather the elephant has left the room. If that’s too cryptic; what is the point of going to all that trouble to promote the technology of designing in 65- or 45-nm silicon when there are only a handful of people in Europe who care? If you were to write down the names of everyone in Europe involved in the mechanics of 65/45-nm digital SoC design, I should think it would fit comfortably on one sheet of paper. If you set aside those easily-targeted design teams that are within the obvious large semiconductor houses, the sheet would be even more sparsely filled: if you refined it to those EDA-tool managers with purchasing authority for that class of tool, in the European arena, you are getting to back-of-a-postage-stamp territory. By the time we get to 22-nm design rules, it will probably be a handful of sheets of paper for the entire world.

Once upon a time, you were all going to be doing designs based around customised SoCs, buying your IP in pret-a-porter chunks from catalogues of perfectly-functioning blocks, stitching them together in smoothly-functioning tool suites and awaiting the delivery of your bespoke slivers of silicon.

Dream on.

The grotesque upward spiral in the cost of developing and fabricating nanometre silicon soon killed off that concept. We leave it to the big semiconductor houses to beat themselves up with the problem, and deliver us versatile ASSPs. And guess what; all of the tool vendors know all of their designers, or at least all their CAD managers; they probably know their shoe sizes, and the given names of their firstborn – so why bother the rest of us with this arcane stuff?

So there’s my opening line for everyone who thrusts an info pack in my direction at DATE; first of all, convince me that those with a need-to-know number more than single figures throughout Europe, then we have the basis of a discussion. If you could, in a morning, personally call everyone who might ever buy your software, then….. please, just do so!

Now, shift the ground to mixed-signal designs on a smaller (size of design) scale, in rather less ambitious feature-size processes – then it gets more interesting. There is rather more of that to be found in fabless chip companies and design houses in our patch of the world.

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