100G Ethernet and Interlaken IP cores for FPGAs

November 20, 2013 // By Graham Prophet
Altera's intellectual property for high-capacity transmission and backhaul applications strengthen, the company says, its portfolio with highest-performance, lowest-latency and smallest resource area comms functions

Four IP cores have been added to Altera's MegaCore IP library, including ultra-high performance and ultra-low latency 100G Interlaken, 100G Ethernet, 40G Ethernet and 10G Ethernet IP. Developers of data centers and networking equipment can use these solutions to increase system bandwidth while differentiating their end system. The Interlaken and Ethernet IP cores, as well as other standard interface IPs, are currently available and fully supported in the latest release of the Quartus II software v13.1.

All IPs included in the MegaCore IP library are validated and demonstrated in silicon. The IP cores deliver 15% timing margin for faster timing closure, which allow customers to quickly integrate multiple IP cores into their designs. The new Interlaken and Ethernet IP cores are optimised for use in Altera’s Stratix V FPGA as well as future Generation 10 FPGAs and SoCs. Customers today via early access software are using these best-in-class IP cores in 20 nm Arria 10 FPGAs.

The new IP cores included in the MegaCore IP library include:

• Low Latency 100G Interlaken IP Core, which uses a soft PCS to deliver roundtrip latency under 200 nsec.

• Low Latency 100G Ethernet IP Core, the smallest 100G Ethernet core, at 55% smaller than the existing 100G Ethernet IP with a roundtrip latency of 160 nsec, making it 70% lower latency than competitive 100G Ethernet IP cores.

• Low Latency 40G Ethernet IP Core – 40% smaller and 60% lower latency than existing 40G Ethernet IP cores.

• Low Latency 10G Ethernet IP Core – 20% smaller and 24% lower latency than any existing 10G Ethernet IP core.

Altera; www.altera.com/ip