1200V SiC MOSFET in low-inductance package

February 27, 2017 // By Graham Prophet
Wolfspeed, part of Cree, has expanded its C3M silicon carbide device platform with a 1200V, 75 mΩ (on-resistance) MOSFET a low-inductance discrete package the company also recently released.

The new FET simplifies designs and enables an increase in frequency while maintaining efficiency, lowering system cost, reducing circuit EMI, and enabling 99% efficiency levels in three-phase power factor correction circuits. Use it, the company suggests, in telecom power supplies, elevators, grid-tied storage, on and offboard EV charging, with faster switching frequency to cut system size and bill of materials.


This device claims the industry’s lowest figure-of-merit for any SiC MOSFET at 1200V. Wolfspeed has released this device in a 4-lead TO-247 package (C3M0075120K) and plans to release it in a 7L D2PAK ( C3M0075120J) shortly. Both packages have a 4 th lead, Kelvin connection.


“SiC MOSFETs have proven to be beneficial for many high-power applications connected to a battery simply due to the improved efficiency.” explains John Palmour, Wolfspeed’s CTO. “In the case where power is bidirectional, such as grid-connected AC-DC, the potential cost savings are significantly increased due to the reduction in the size of the input filter.”


The device employs Wolfspeed’s third generation C3M planar MOSFET technology, which features low on-resistance combined with a low gate charge; the new package designs allow engineers to take advantage of the technology's high-frequency capability. The 4L TO247 package delivers a 3x reduction in total switching losses compared to a conventional TO-247-3 package.


The 7L D2PAK surface-mount package, specifically designed for high-voltage MOSFETs, substantially eliminates the source inductance found in other packages and has a footprint 52% smaller than D3PAKs, exploiting the small die size and high-blocking capability of C3M planar MOS technology.


Designers can, Wolfspeed says, reduce component-count by moving from silicon-based, three-level topologies to simpler two-level topologies made possible by the improved switching performance. These higher voltage SiC MOSFETs solve many of the limitations of silicon super-junction MOSFETs that make them impractical to use in two-level topologies. SiC has significantly lower output capacitance non-linearity, making it possible to reduce the dead-time thereby minimizing total