The parts feature a range of integrated functions to help you exploit their performance, and to simplify their use; the “breakthrough performance, bandwidth, and integrated functionality” will drive applications further towards direct-RF sampling, ADI asserts.
AD9680 is a dual-channel, 1.25-V,14-bit, 1-Gsample/sec A/D converter featuring the best noise and dynamic range performance in its class enabling the trend for direct RF sampling in communications, instrumentation and military/aerospace applications. Its noise density of -154 dBFs/Hz is the lowest in the industry. Wideband RF data acquisition allows for better signal extraction in congested RF environments, over a wider bandwidth; the device also features four digital down-converters to assist with isolating a specified fraction or subset5 of the overall bandwidth. The AD9680 is interoperable with FPGAs from major manufacturers and supported with known good configurations, and offers ease of interfacing.
The AD9680, ADI says, allows more degrees of freedom for system designers trading off signal bandwidth, noise and linearity because it can digitise a DC to 2-GHz input signal with an accompanying dynamic range performance that was previously unavailable on the open market. You can increase signal sensitivity and bandwidth data rate, while enabling the use of an advanced reconfigurable data acquisition or radio platform. The A/D converter is available with an evaluation board design environment and reference designs for rapid system prototyping and board-level design and layout.
The AD9680 was designed for sampling wide bandwidth analogue signals up to 2 GHz with best-available dynamic range and noise performance over its rated bandwidth range. When converting a 1-GHz input, the converter achieves spurious-free dynamic range (SFDR) performance of 80-dBc and 61.5-dBFS signal-to-noise ratio (SNR) while consuming 1.65 W of total power per channel. Integrated functionality includes digital signal processing blocks and a configurable JESD204B interface, allowing designers to create advanced reconfigurable radio platforms that meet bandwidth and cost requirements across multiple systems. Higher speed grades are scheduled. On-chip features support signal monitoring and threshold detection prior to the signal being passed to an FPGA, speeding reaction and reducing the digital processing load.
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