The Xilinx UltraScale devices support the full HMC bandwidth of 4 lanes, comprised of 64 transceivers running up to 15 Gb/sec. Pico Computing's HMC controller IP yields high memory bandwidth and performance/watt in a small but modular and highly scalable footprint. The combined solution enables engineers to begin 15 Gb/sec HMC designs for applications in domains such as high performance computing, packet processing, waveform processing, and image and video processing.
Hybrid Memory Cube is a high performance memory solution that delivers unprecedented levels of bandwidth, power efficiency, and reliability. Xilinx says that, “UltraScale FPGAs are the only devices currently available that can support all four HMC lanes to enable full memory bandwidth with additional transceivers for datapath and control signals.”
Pico Computing’s HMC controller is highly parameterised to yield an optimised system configuration to meet specific design objectives. The number of HMC links addressed, the number and width of internal ports, clock speeds, power, performance, area, and other parameters can be “dialed in” to yield precisely the performance required.
“Pico Computing’s HMC controller IP, now optimised and implemented on Xilinx UltraScale devices, creates an extremely efficient and flexible system solution,” said Jaime Cummins, CEO at Pico Computing. “This enables both the HMC and UltraScale devices to perform at their highest levels, which in turn, enables whole new classes of high-performance computing applications.”