1.5-V PCI Express clock buffers cut power drain

July 25, 2014 // By Graham Prophet
IDT describes its ultra-low-power PCIe buffers as “SoC-friendly” - they use the same 1.5V rail as today’s SoCs, reducing system complexity, size, and power

Added to a PCIe timing portfolio are the first 1.5 V PCI Express (PCIe) buffers. IDT's U-series ultra-low power PCIe buffers operate from the same supply voltage as stems-on-chip (SoCs) and field programmable gate arrays (FPGAs). The 9DBU buffers come in 2 to 9-output configurations to address virtually any PCIe application. Both non-PLL fan out and PLL zero-delay-buffer modes are supported. The new timing solutions are an addition IDT’s V-series of 1.8V PCIe clocks for communications, computing, and consumer markets.”

Device options include external or internal terminations, allowing designers to choose between maximum flexibility with external termination circuitry, or maximum space savings using internal terminations. The entire family operates from a 1.5V supply, with eight-output devices using 40 mW. The 1.5 V U-series devices are pin-compatible with IDT’s 1.8V V-series, allowing for easy substitution as SoC operating voltages continue to drop. The 9DBU buffers are compliant with PCIe Gen 1, 2, and 3 so designers can use the same component through several generations of product.

Idt; www.idt.com/go/PCIe