The ADC requires a single 1.8 V power supply and an LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. For many applications, no external reference or driver components is required.
The AD9249 automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. Data clock outputs (DCO±1, DCO±2) for capturing data on the output and frame clock outputs (FCO±1, FCO±2) for signalling a new output byte are provided. Individual channel power-down is supported, and the device typically consumes less than 2 mW when all channels are disabled.
The ADC contains several features designed to maximise flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation; available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). The device comes in a 144-ball CSP-BGA and operates over the industrial temperature range of −40°C to +85°C.
SNR: 75 dBFS (to Nyquist); SFDR: 90 dBc (to Nyquist)
DNL: ±0.6 LSB (typical); INL: ±0.9 LSB (typical)
Crosstalk, worst adjacent channel, 10 MHz, −1 dBFS: −90 dB typical
Small footprint; sixteen ADCs are contained in a small, 10 mm × 10 mm package.
Low power of 35 mW/channel at 20 MSPS with scalable power options (for example, 58 mW per channel at 65 MSPS
Ease of use; data clock outputs (DCO±1, DCO±2) operate at frequencies of up to 455 MHz and support double data rate (DDR) operation.
Flexibility; SPI control offers a wide range of flexible features to meet specific system requirements.