Integrating a Spartan-6 FPGA with a PCI Express endpoint along with two mDDR low power memories, one SPI NOR flash for secure boot and 167 decoupling capacitors in one single device, the company is offering designers a drastically reduced footprint, with a reduced pin count of 484 balls compared with the original FGPA footprint of 676 balls.
Compared to the overall footprints of the memories, FPGA and decoupling capacitors taken separately, the Fusio-II provides a footprint reduction from 937 mm 2 down to 361 mm 2 (without taking account of extra layout space needed for high speed signal integrity).
The fully tested and validated subsystem can be directly placed on a board and connected to dedicated peripherals.
Fusio-II main characteristics:
Xilinx Spartan-6 XQ6SLX150T FPGA with high speed serial connectivity offering an integration of up to 147,443 logic cells.
4 High speed GTP serial transceivers characterised at 2.5 Gbps, which can be configured as a PCI-express endpoint.
2 x 128 Mbits of low power mDDR operating at 166 MHz.
167 decoupling caps providing optimum filtering for each of 10 power supplies
203 multi-purpose User I/O through three independent banks
The Fusio-II module comes in commercial (0-70°C) and industrial (-40°C/ +85°C) temperature range.
3D PLUS; www.3d-plus.com