20-nm FPGAs shift to fine-pitch copper bump technology to meet interconnect needs

April 22, 2014 // By Graham Prophet
Altera and TSMC have announced that they are to use TSMC’s fine-pitch copper bump-based packaging technology for Altera’s 20 nm Arria 10 FPGAs and SoCs. Altera is the first company to adopt this technology in commercial production to deliver improved quality, reliability and performance.

“TSMC has provided a very advanced and robust integrated package solution for our Arria 10 devices, the highest-density monolithic 20 nm FPGA die in the industry,” said Bill Mazotti, vice president of worldwide operations and engineering at Altera, adding that it, “... helps us address the packaging challenges at the 20 nm node.”

TSMC’s flip chip BGA package technology provides Arria 10 devices with better quality and reliability than standard copper bumping solutions through the use of fine-pitch copper bumps. The technology is able to accommodate very high bump counts as required by high-performance FPGA products. It also provides excellent bump joint fatigue life, improved performance in electro-migration current and low stress on the ELK (Extra Low-K) layers, all highly critical features for products employing advanced silicon technologies.

“TSMC’s copper bump-based package technology provides excellent value for small bump pitch (<150 µm) advanced silicon products featuring ELK,” said David Keller, senior vice president, business management, TSMC North America.

Altera; www.altera.com

TSMC’s copper bump-based package technology is scalable for products that feature large die size and small bump pitch. It includes a DFM/DFR implementation from TSMC that adjusts package design and structure for wider assembly process windows and higher reliability. The technology has demonstrated better than 99.8% production-level assembly yields; www.tsmc.com