20-nm programmable silicon will support 32-Gbps transceivers – Altera

April 08, 2013 // By Graham Prophet
Altera has announced that it has succeeded with a laboratory demonstration of a programmable device with 32-Gbps transceiver capabilities. The demonstration uses a 20-nm device based on TSMC’s 20SoC process technology.

This, the company says, validates the performance capabilities of 20-nm silicon, adding that it has over 500 customers in its early access program who are looking to use next-generation Altera devices in the development of performance demanding, bandwidth-centric applications. A demonstration video showing the industry’s first operational 20 nm transceiver technology operating at 32 Gbps is available for viewing on Altera's website at www.altera.com/32gbps-20nm

Demonstrating 32-Gbps transceiver data rates provides Altera insight into how high-performance transceiver designs behave on TSMC's 20SoC process. The transceiver technology will be integrated into its 20 nm FPGA products; Altera claims to be the only company today shipping production 28-nm FPGAs with monolithically integrated low-power transceivers operating at 28 Gbps.

The demonstration video on Altera’s web site shows 20-nm transceivers operating at 32 Gbps with just over 9 psec of total jitter and extremely low random jitter of 240 fsec. The results show good margin to key industry specifications requited for next-generation 100G systems. Vince Hu, vice president of product and corporate marketing at Altera, comments, “These 20 nm devices contain the key IP components that will be included in our next-generation FPGAs and validating them now provides us confidence we will deliver to the market 20 nm FPGAs on schedule.”

The transceivers in Altera’s next-generation devices will drive more bandwidth with lower power per channel versus the previous nodes and will also be able to support increasing port density by interfacing directly to 100G CPF2 optical modules.