- Automatic electromagnetic (EM) simulation setup and design partitioning, which automates the removal of SMD and IC active devices, and placement of ports, then reconnection of the design, in under one-tenth of the time and with fewer than one-twentieth mouse clicks.
- Physical layout-versus-schematic (LVS) with device recognition and a module-level LVS that uncovers multi-technology wiring and pin-swap errors.
- Wireless verification test benches that provide circuit design verification solutions for the newest and most challenging multi-band, wide-bandwidth standards (LTE, LTE-A and 802.11ac) with a dramatically simplified user interface.
- Improved layout interconnect design and editing capabilities, including new power and ground planes with smoothing and thermal relief, new intelligent vias and interconnect routes.
- Controlled Impedance Line Designer for quickly and accurately optimising stack-up and line geometry for multi-gigabit-per-second chip-to-chip links.
- Silicon RFIC schematic interoperability with Virtuoso for bi-directional schematic interoperability between ADS and Cadence Virtuoso.
- ADS Board Link, the next-generation printed circuit board integration solution for bi-directional transfer of layouts, schematics and libraries between ADS and enterprise PCB tools.
- Simulation support for Agilent’s DynaFET model, an advanced neural network model for III-V FETs (GaAs and GaN), to accurately model the effects of trapping, de-trapping, and self-heating, in a single, global model, valid for all (active) applications, without the need for tuning.