32 Gbit/sec BERT gains clock recovery options

May 08, 2014 // By Graham Prophet
Clock Recovery options for Anritsu’s MP1800A Signal Quality Analyser (SQA) provide for Bit Error Rate (BER) testing of high-speed interconnects at up to 32.1 Gbit/sec with a single instrument.

High-speed serial communications equipment use components such as SERDES devices, Active Optical Cables (AOC) and optical transceiver modules, which send and receive serial data without transmitting synchronous clock signals. Previously, BER and jitter tolerance measurements of these systems required an external clock recovery instrument. With the introduction of the internal Clock Recovery options for the MP1800A, users can perform these measurements with a single box.

The MP1800A is a modular-type BERT composed of a Pulse Pattern Generator (PPG), plus a high input-sensitivity Error Detector (ED). A jitter modulation source may be installed in the instrument to generate various types of jitter, enabling users to test a device’s jitter tolerance.

To increase processing speeds, high-performance servers in data centres are standardising on high-speed serial communications methods exceeding today’s 25 Gbit/sec data rates, such as 100GbE (100G Base CR4, KR4), InfiniBand EDR, CEI-28G, 32G FC and others. Trunk communications networks are developing next-generation transmission technologies supporting data rates of 400 Gbit/sec. Anritsu developed its MP1800A Signal Quality Analyser as a platform for evaluating the high-speed interconnects found in such equipment, and it already supports BERT and jitter measurements up to 32 Gbit/sec. Installing the new Clock Recovery options strengthens its capabilities, providing for clock-less device BER measurements and jitter tolerance measurements, and leading to more accurate signal-integrity analyses across a wide range of applications.

Anritsu; www.anritsu.com