The HMC1033LP6GE is ideal for clocking DSP, FPGA and high performance processors as well as physical layer devices, and operates from 25 MHz to 550 MHz. The HMC1035LP6GE is designed to meet the stringent requirements of high speed data converters (ADC/DAC) with excellent phase noise floor performance of -162 dBc/Hz, and operates from 25 MHz to 2.5 GHz.
Both devices require only a single 3.3 V supply rail and achieve up to 33% reduction in power consumption compared to previous solutions. They feature a flexible output buffer, which can be programmed via the serial programming interface (SPI) to support 12 different output amplitude settings including those for LVDS-compatible, and LVPECL signaling. A proprietary ‘Exact Frequency Mode’ of operation reduces frequency errors in fractional-N synthesis mode while maintaining excellent noise and spur performance.
Both products offer two modes of operation to trade off performance in favor of reduced power consumption. These two modes are defined as “Power Priority” and “Performance Priority” and may be selected via the SPI registers. In the “Power Priority” mode, the HMC1035LP6GE sources 173 mA typical current from the 3.3 V supply with 2.5 GHz LVDS-compatible outputs, and in “Performance Priority” mode, the device achieves an integrated phase jitter performance of 100 fs RMS typical (12 kHz to 20 MHz integration bandwidth, 2.5GHz outputs), and improves interface Bit-Error-Rates (BER ) and eye diagram metrics. Both devices also produce an excellent 49 to 51% output duty cycle on their differential output.
The HMC1033LP6GE and the HMC1035LP6GE may be used to generate the sample clocks for high speed data converters (ADCs and DACs) in cellular infrastructure and fiber optic applications. With their very low phase noise floor, the clock generators improve the SNR of data converters by providing very clean sample and device clocks.
Both clock generators are each assembled in 6 x 6 mm plastic leadless surface mount packages, and support operation over the -40 °C to +85