3D memory chips may beat 3D hybrid memory cube

October 01, 2015 // By R. Colin Johnson
A novel three-dimensional (3D) memory from the self-described "nanotechnology development center" with its own fab to boot will make an appearance next week at SEMICON Europa 2015.

Novati Technologies Inc. (Austin, Texas)—a wholly owned subsidiary of Tezzaron Semiconductor—will show its latest foray into 3D chips that combine memory, logic, microelectromechanical systems (MEMS) and other sensors/actuators into one system-in-package (SiP) Integrated Sensor Platform for the Internet of Things (IoT).

The SiPs, which stack 20-micron thinned die into a package the same size as a traditional planar chip, will be shown at SEMICON Europa 2015 (Oct. 6-8, Dresden, Germany).

"We can thin die and stack them into multilayers of memory, logic, analog and sensors," David Anderson chief executive officer of Novati told EE Times in an exclusive interview. "For instance, we built a high-energy photon detector for Fermi Labs using logic and sensor on the same stack which reduced parasitics enough to double performance while reducing packaging costs."

Novati can manufacture heterogeneous 3-D chip or incorporate 2.5-D interposers.(Source: Novati, used by permission)
Novati can manufacture heterogeneous 3-D chip or incorporate 2.5-D interposers.

(Source: Novati, used by permission)

Tezzaron/Novati is practicing transistor-level 3D—what they call Di3D (Dis-Integrated 3D) and now considers itself an expert in the integration of heterogeneous chips by wafer bonding—without spacers between the dies as used my Microjn and Hynix. Tezzaron/Novati are working toward its next milestone of 18 stacked die (including two CMOS logic layers)—the DiRAM4, a 64Gb very high performance RAM with double the memory capacity of its current eight-layer offering.

"We can stack back-to-front or front-to-back plus we can can uses interposers when necessary. Most vertical connections among die are done with through-silicon-vias (TSVs), but we have various other ways to make connections while bonding with an accuracy of a couple of microns," Anderson told EE Times.

For instance, Tezzaron/Novati's TSV-free wafer stacking uses tungsten "SuperContacts" whose vertical interconnect density in the stack that is at least 60 times the density of TSVs. Because of this the companies can dis-integrate circuits and spread them vertically across multiple wafers. As a result, Tezzaron/Novati puts less circuitry per wafer instead of more, and it can use the right substrate for the transistor being used, instead of making do with the transistor that a certain substrate can handle, with a peak bandwidth of 8-terabits per second.