Using a stacked cell structure, the 64-layer device achieves its 512-gigabit (64-gigabytes) capacity with 3-bit-per-cell (triple-level cell, TLC) technology. The device will be used in applications that include enterprise and consumer SSD. Sample shipments of the chip started early in 2017, and mass production is scheduled for the second half of the calendar year.
Toshiba says it is continuing to refine BiCS FLASH, and the next milestone on its development roadmap is the industry’s largest capacity, a 1-terabyte product with a 16-die stacked architecture in a single package. Plans call for the start of sample shipments in April 2017.
For the 512-gigabit device, Toshiba used an advanced 64-layer stacking process to realize a 65% larger capacity per unit chip size than the 48-layer 256-gigabit (32-gigabytes) device [that it already produces], and has increased memory capacity per silicon wafer, reducing the cost per bit.
Toshiba’s memory business already mass produces 64-layer 256-gigabit (32-gigabytes) devices and will expand BiCS FLASH production. The company says it will advance 3D technology to realize increased densities and finer [smaller geometry] processes in order to meet diversifying market needs.