Footprint-compatibility in these DC/DC units provides increased flexibility in power system design. The two added modules offer high performance without compromising on dynamic response; the auto-compensated digital POL regulators are based on ‘state-space’ or ‘model-predictive’ control, reducing cost and time-to-market while increasing flexibility
These modules also have Dynamic Loop Compensation (DLC), advanced energy-optimisation algorithms to reduce energy consumption, low-bias current technology, and a land-grid-array (LGA) footprint that guarantees excellent thermal, mechanical and electrical performance.
A feature of the two new modules is that they are 100% footprint compatible with the existing 12A BMR4613001 product; three different output currents – 6A, 12A and 18A – are available while only having to handle a single module footprint in new systems. This simplifies board design and makes it easier for power architects to move to higher or lower current-handling power modules without needing to redesign the system board when upgrading to new microprocessors or other advanced logic devices such as FPGAs or ASICs.
The BMR4614001 module is optimised to deliver 18A at 1.8V, making it suitable for processors operating at sub-2V core voltages. It is the first product of its kind to deliver this level of output current in a 12 x12mm footprint, while also delivering automatic loop compensation and full PMBus command capability.
The Dynamic Loop Compensation integrated into the 6A BMR4612001 and 18A BMR4614001 is based on “state-space” or “model-predictive” control, which guarantees stability while also achieving the optimum dynamic performance without requiring any external components. The new products perform an automatic compensation routine based on measured parameters, which enables the construction of an internal mathematical model of the power supply including external components such as filtering and parasitic resistors. Based on the ‘state-space’ mathematical model rather than traditional proportional-integral-derivative (PID) regulation, the devices use closed-loop pole placement and a model based on the resonant frequency of the output filter, thereby reducing the number of output capacitors required for filtering and stability. This technology is suitable for FPGA and processor applications where low-ESR decoupling capacitors are used currently.