Accelerate SoC prototyping on Xilinx Virtex-7 FPGA-based FPGAs with partitioning tool

April 16, 2013 // By Julien Happich
Flexras Technologies has released version 3.2 of its Wasga Compiler Design Suite for FPGA-based prototyping. This new release supports the Xilinx Virtex-7 FPGA and includes new features that accelerate SoC rapid prototyping.

“Collaboration with Xilinx has allowed us to optimise our partitioning flow for next-generation SoC implementations based on Virtex-7 All Programmable FPGA-based prototyping systems,” said Hayder Mrabet, CEO of Flexras Technologies. “With its timing-driven automatic partitioning and high speed Virtex-7 FPGA Advanced Pin Multiplexing (APM) IP for inter-FPGA communications, Wasga Compiler enables very fast prototyping of complex SoCs, achieving efficient results in days, or even hours.”

The Wasga Compiler now includes Virtex-7 FPGA Advanced Pin Multiplexing IPs (APM) using both Serdes and LVDS I/O. The tool supports the automatic generation of XDC pin-planning and timing constraints for the Vivado Design Suite. It performs logic replication and pruning to optimise connectivity between FPGAs and includes models for inter-FPGA configurable cables. The Wasga Compiler Design Suite supports Dini boards, including the DNV7F2A. It is also included in Reflex's FPP25 offering.

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