The Speedster22i FPGA family is built on Intel’s 22nm Tri-Gate process technology and consists of three device members, two of which have entered production – the HD680 with 660 thousand effective look-up-tables (LUTs) and the HD1000 with 1 million effective LUTs.
Speedster22i FPGAs use the Intel finFET production process technology node, and are positioned as having the greatest amount of “hardened” interface IP currently available. The HD1000 has two 100 Gigabit Ethernet controllers, two 120 gigabit Interlaken controllers, two PCIe Gen3 x8 controllers and six 1866 Mbps DDR3 controllers. All of these are complete in the silicon and do not use programmable resource: the would use 350,000 LUTs of logic if implemented in the programmable fabric. In addition to freeing up the programmable fabric, the hardened IP also speeds up development time because the IP meets timing and does not need to be placed and routed. The HD1000 also has 86 Mbit of on-chip RAM, 64 high performance SerDes lanes and almost a thousand programmable I/O.
“Developing high-end FPGAs with up to six billion transistors is complex and challenging,” said Steve Mensor, Vice President Marketing, Achronix. “Achronix FPGAs with hard IP targeted for high performance wireline applications that are now in production offer a lower power and lower priced solution than the alternative general purpose FPGAs from other vendors.”
The Speedster22i family is supported by the Achronix CAD Environment (ACE) tool suite, which includes Synplify Pro for Achronix from Synopsys. Achronix also has development boards and a range of reference designs that accelerate development times and help customers reduce their time-to-market challenges.
Achronix Semiconductor; www.achronix.com