ADC provides highest dynamic performance to maximize receiver sensitivity

November 01, 2012 // By Paul Buckley
Texas Instruments Incorporated has introduced a pair of devices today supporting the JEDEC JESD204B serial interface standard for data converters.

The ADS42JB69 claims to be the industry’s first dual-channel, 16-bit analog-to-digital converter (ADC) featuring the JESD204B interface and is also the fastest at 250 MSPS. The LMK04828 is the industry’s highest-performance clock jitter cleaner and is the first to support JESD204B clocking. When used together, the devices provide unmatched system-level performance for high-speed systems. For designs requiring a traditional parallel interface, the company also introduced the ADS42LB69, the industry’s fastest dual, 16-bit ADC at 250 MSPS featuring an LVDS interface.

JESD204B is an industry-standard serial communications link that simplifies the digital data interface between data converters and other devices, such as FPGAs, DSPs and ASICs. The standard reduces the routing between devices, slashing input/output and board space requirements for applications, such as wireless communications, test and measurement, and defense and aerospace.

The ADS42JB69 maximizes flexibility in system design, because it is the only 16-bit ADC incorporating all three JESD204B subclasses, 0, 1 and 2, allowing multi-device synchronization between data converters. The ADS42JB69 also supports the new JESD204B standard for deterministic latency, which provides fixed transmission delay with or without the use of an external timing signal. The device is also compatible with the existing JESD204A standard.

At 170 MHz intermediate frequency, both ADCs provide spurious-free dynamic range (SFDR) performance of 89 dBc, up to 9-dB better than the competition, along with SFDR of 100 dBc, excluding harmonic distortion 2 (HD2) and HD3, signal-to-noise ratio (SNR) performance of up to 74.9 decibels relative to full scale (dBFS) and channel isolation of 100 dB.

ADS42JB69 with JESD204B interface reduces the required number of data interface lanes from 17 to five, slashing board space while reducing design complexity.

ADS42LB69 supports traditional parallel interface designs via 17 lanes of double data rate (DDR) low-voltage differential signaling (LVDS) or 10 lanes of quad data rate LVDS.

The ADS42JB69 consumes 775 mW/channel, while the ADS42LB69 uses only 740 mW/channel.

The new ADCs are part of a