The AD9234 is optimised for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. Its dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth buffered inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate-by-2 block.
The AD9234 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an over-range condition at the ADC input. In addition to the fast detect outputs, the AD9234 also offers signal monitoring capability, with a signal monitoring block that provides additional information about the signal being digitised.
Users can configure the Subclass 1 JESD204B-based high speed serialised output in a variety of one-, two-, or four-lane configurations, depending on the acceptable lane rate of the receiving logic device and the sampling rate of the ADC. Multiple-device synchronisation is supported through SYSREF± and SYNCINB± input pins.
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