ADI simplifies high-speed data converter-to-FPGA interconnect design

October 08, 2012 // By Jean-Pierre Joosting
Communications infrastructure, imaging equipment, industrial instrumentation, defence electronics and other multi-channel, data-hungry systems are demanding wider resolutions and higher sampling rates from the data conversion stage. Physical layout constraints of the parallel interface and bit-rate limitations of the serial LVDS (low-voltage differential signalling) approach are beginning to present technical barriers for designers.

To address this need, Analog Devices has introduced the AD9250 dual-channel, 14-bit, 250-MSP A/D converter featuring the JEDEC JESD204B serial output data interface standard. The AD9250 A/D converter claims to be the first-to-market with full JESD204B Subclass 1 deterministic latency at 250 MSPS. This functionality accommodates the precise synchronisation of multiple data-conversion channels through a serial interface.

The AD9250 A/D converter’s serial interface implementation provides up to 5 Gbps over a 1 or 2 lane-capable link. Two serial lanes are used to support the full 250-MSPS, dual A/D converter data rate, or a single lane can be used to support reduced sampling rates.

High-performance FPGA suppliers, such as Xilinx, have incorporated on-chip JESD204B SerDes (serialiser/deserialiser) ports into their latest generation products. This end-to-end seamless connectivity for the analog signal chain results in simplified PCB layout, rapid prototyping capability, and faster time-to-market.

The AD9250 converter’s JESD204B serial interface reduces the number of high-speed differential output data paths required from as many as 28 to just two per IC. Its Subclass 1 deterministic latency function is repeatable from power-up cycle to power-up cycle and across link re-synchronisation events. Areas where this function is important are in diversity radio systems and instrumentation, multi-mode digital receiver applications such as TD-SCDMA, WCDMA, LTE (especially the 2R2T >8R8T evolution), radar/defence electronics, medical imaging systems, cable infrastructure and general-purpose software radios.

Key features of the AD9250 include JESD204B coded serial digital output with Subclass 1 deterministic latency; SNR of 70.6 dBFS at 185 MHz AIN and 250 MSPS; SFDR of 88 dBc at 185 MHz AIN and 250 MSPS; IF sampling frequencies of up to 400 MHz; 95-dB channel isolation/crosstalk; low power and small package size

The AD9250-250EBZ (250 MSPS), AD9250-170EBZ (170 MSPS), and AD6673-250EBZ DUT boards, and companion HSC-ADC-EVALDZ high-speed data capture card, comprise a signal performance-optimised complete evaluation system for the AD9250. The captured data can be analysed using a laptop computer and ADI’s free