The demonstration provides an “early proof point” that production support of HMC will be delivered with Altera’s Generation 10 portfolio, and includes both Stratix 10 and Arria 10 FPGAs and SoCs.
HMC is promoted as a means of addressing the limitations imposed by conventional memory technology, providing high system performance with significantly lower power-per-bit. HMC delivers up to 15 times the bandwidth of a DDR3 module and uses 70% less energy and 90% less space than existing technologies. HMC’s abstracted memory allows designers to devote more time making use of HMC’s features and performance and less time navigating the multitude of memory parameters required to implement basic functions. It also manages error correction, resiliency, refresh, and other parameters impacted by memory process variation. Micron expects to begin sampling HMC later this year with volume production beginning in 2014.
Layers of a HMC stack build-up.
Altera’s 28 nm Stratix V FPGAs can exploit the full bandwidth, efficiency and power benefits of HMC by using a full 16 transceiver HMC link.
“By demonstrating Stratix V and HMC working together now, we are enabling our customers to leverage their current development with Stratix V FPGAs and prepare for production deployment in Altera’s Generation 10 devices, knowing they will have proven HMC support,” said Danny Biran, senior vice president of marketing and corporate strategy at Altera.
Arria 10 FPGAs and SoCs are the first device families in the Generation 10 portfolio and will use HMC to extend the benefits by providing both 15% higher core performance than today’s highest performance Stratix V FPGAs and up to 40% lower power compared to the lowest power Arria V midrange FPGAs. Arria 10 FPGAs and SoCs will offer up to 96 transceiver channels, enabling users to take full advantage of the bandwidth that HMC has to offer.
Stratix 10 FPGAs and SoCs will seek applications across communications, military, broadcast and compute and storage markets, in designs that