The 14 nm-based FPGA test chips incorporate key intellectual property (IP) components – transceivers, mixed-signal IP and digital logic – used in Stratix 10 FPGAs and SoCs. Altera and Intel collaborated on the development of the industry’s first FPGA-based devices exploiting Intel’s process technology and Altera’s programmable logic technology.
This follows established pattern of announcing, in each generation, first the technology that it will deliver, then at a later stage, the actual product, or as the company says, it has “...a comprehensive test chip program to de-risk the rollout of all its next-generation products by validating how Altera IP performs using innovative process improvements and circuit design techniques prior to final product tape out.” Through the use of multiple 14-nm devices, Altera sees very positive results in the high-speed transceiver circuitry, digital logic and hard-IP blocks that will be used in Stratix 10 FPGAs and SoCs.
Intel says it has a “true die shrink” with its second-generation 14 nm Tri-Gate process, relative to alternative FinFET technologies. In Intel’s 14 nm Tri-Gate process and an enhanced high-performance core fabric architecture, Stratix 10 FPGAs and SoCs will target advanced, high performance applications in the communications, military, broadcast and compute and storage markets, while cutting system power. Core operating performance will be up to 1 GHz. For high-performance systems that have the most strict power budgets, Stratix 10 devices allow customers to achieve up to a 70% reduction in power consumption by trading performance for power. Promised features include;
• monolithic device with greater than four million logic elements (LEs)
• over 10 TeraFLOPs of single-precision, hardened floating point DSP performance
• more than 4X serial transceiver bandwidth compared to previous generation FPGAs, including 28-Gbps backplane capable transceivers and a path to 56 Gbps transceivers
• quad-core 64-bit ARM Cortex-A53 processor system
• multi-die solutions capable of integrating DRAM, SRAM, ASICs, processors and analog components in a single package.