Altera demonstrates FPGAs running 56 Gbps PAM4 inter-chip traffic

March 22, 2016 // By Graham Prophet
Stratix 10 FPGAs and SoCs, says maker Altera (Intel) are set to enable next-generation data centre and terabit communications applications.

Altera, now the Programmable Solutions Group (PSG) within Intel, has disclosed transceiver technology that it says will enable Stratix 10 FPGAs and SoCs to support data rates up to 56 Gbps. Altera is demonstrating dual-mode 56-Gbps pulse-amplitude modulation with 4-levels (PAM-4) and 30-Gbps non-return-to-zero (NRZ) transceivers. The transceiver technology doubles the bandwidth available on a single transceiver channel, while providing equipment manufacturers scalability to build future systems. Stratix 10 FPGAs and SoCs, Altera says, are optimised to support the massive amounts of data that are being transmitted across copper backplanes and optical interconnects used in data centre infrastructure and telecommunications equipment. The Stratix 10 FPGA transceiver technology will support data rates ranging from 1 Gbps to 56 Gbps. Engineers can use Stratix 10 FPGAs to build next-generation communications and networking infrastructure that support 50G, 100G, 200G, 400G and terabit applications. The transceiver’s dual mode capabilities provide customers a path to develop next-generation high-end systems, while also providing investment protection by supporting mainstream and legacy backplanes, copper cables, chip-to-chip and chip-to-module interconnects and interfaces. Altera has been involved as leader and contributor to the 50G-56G PAM-4 standard within the IEEE 802.3 Ethernet and Optical Internetworking Forum (OIF).


A demonstration video of this transceiver technology showing 56 Gbps PAM-4 and 30-Gbps NRZ backplane is available at


Stratix 10 FPGA transceivers are integrated using a heterogeneous system-in-package (SiP) approach. [Also known as “2.5D integration”] Transceiver tiles are combined with a monolithic FPGA core fabric using Intel’s Embedded Multi-die Interconnect Bridge (EMIB) technology, which allows Stratix 10 FPGAs and SoCs to address the ever-increasing system bandwidth demands across virtually every market segment. A transceiver tile approach offers greater flexibility, scalability and faster time-to-market.


Initial Stratix 10 FPGAs will start shipping in Q4 2016;