Altera design software release adds support for DSP & FPU blocks

December 16, 2014 // By Graham Prophet
Quartus II Software v14.1 enables, Altera says, teraFLOP performance to be achieved in the company’s FPGAs with “hard” floating point arithmetic blocks.

Quartus II v14.1 has expanded support for Arria 10 FPGAs and SoCs, FPGA s with hardened floating point DSP blocks and (in 20 nm technology) integrated ARM processors. Altera's latest software release provides immediate support for the hardened floating point DSP blocks integrated in Arria 10 FPGAs and SoCs. Users can choose between three DSP design entry flows and achieve up to 1.5 TFLOPS of DSP performance. The software also includes several optimisations that improve designer productivity by accelerating Arria 10 FPGA and SoC design time.

Arria 10 FPGAs and SoCs have integrated IEEE 754-compliant, floating-point DSP blocks, the Quartus II software v14.1 offers an advanced tool flow with multiple design entry options that target the hardened floating point DSP blocks and allow users to quickly design and deploy solutions that address a range of computationally intensive applications, in areas such as high-performance computing (HPC), radar, scientific and medical imaging. These design flows include OpenCL for software programmers, DSP Builder for model-based designers and hardware description language (HDL) flows for traditional FPGA designers. Unlike a soft implementation, hardened floating point DSP blocks do not consume valuable logic resources for floating point operations.

Additional Features in Quartus II Software v14.1 Include:

  1. An enhanced Design Space Explorer II (DSE II) tool for faster timing closure, which delivers real-time status and reporting data to users. The data can be used to do side-by-side comparisons of multiple compiles being generated simultaneously on compute farms.
  2. An optimised centralised IP catalogue and improved graphical user interface (GUI) helps to store and easily find all custom IP in a single location.
  3. Additional support for Altera’s non-volatile MAX 10 FPGAs, which feature dual-configuration flash, analogue and embedded processing capabilities in a small-form-factor, low-cost, instant-on programmable logic device.
  4. Enhancements to the JNEye serial link analysis tool simplify board-level design and planning. The JNEye tool, along with Arria 10 silicon models, is able to simulate transmission line models and estimate insertion loss and cross talk parameters in Arria 10 designs.