Integrating hardened IEEE 754-compliant, floating-point operators in an FPGA, delivering greater levels of DSP performance, designer productivity and logic efficiency. The hardened floating point DSP blocks are integrated in Altera’s 20 nm Arria 10 FPGAs and SoCs – currently shipping – and will be in its 14 nm Stratix 10 FPGAs and SoCs. Integrated hardened floating-point DSP blocks, combined with an advanced high-level tool flow, enable you to use Altera’s FPGAs and SoCs to address an expanding range of computationally intensive applications, such as high-performance computing (HPC), radar, scientific and medical imaging.
The hardened single-precision floating point DSP blocks included in Arria 10 and Stratix 10 devices are based on Altera’s variable precision DSP architecture. Unlike traditional approaches that implement floating point by using fixed point multipliers and FPGA logic, Altera uses efficient, hardened floating point DSP blocks to eliminate nearly all the logic usage required for existing FPGA floating-point computations. This yields up to 1.5 TeraFLOPs (floating point operations per second) DSP performance in Arria 10 devices and up to 10 TeraFLOPs DSP performance in Stratix 10 devices, the company asserts. DSP designers are able to choose either fixed or floating-point modes and the floating point blocks are backwards compatible with existing designs.
FPGAs feature a fine-grained, highly pipelined architecture that make them ideally suited for use as high-performance compute accelerators. The inclusion of hardened floating-point DSP blocks enable customers to use Altera FPGAs to address more complex HPC problems in big data analytics, seismic modelling for oil and gas industries and financial simulations. Across these and many other computationally intensive applications, FPGAs deliver the highest performance per Watt when compared to DSPs, CPUs and GPUs, Altera adds.
Altera further claims that you can also save development time by upwards of 12 months. Designers can translate their DSP designs directly into floating-point hardware, rather than converting their designs to fixed point. As a result, timing closure and verification times