In an announcement – that was previously scheduled – which was issued immediately after the confirmation that Intel intends to acquire Altera, the FPGA maker disclosed further architectural and product details of its forthcoming Stratix 10 FPGAs and SoCs, the first samples of which will be available in late 2015. Altera had already told us that its, “next generation of high-end programmable logic devices delivering breakthrough levels of performance, integration, density and security,” would be built on Intel’s 14 nm Tri-Gate (finFET) process, and would include ‘hard’ ARM Cortex A53 cores in their “SoC” guise. This announcement fleshes out some of the detail, adds some performance points – that are derived largely from simulations, at this time – and clarifies the way that the most complex parts will be built on Intel’s technology. The latter aspect, Altera emphasises, was the result of the long-term cooperation between the two, and is not driven by the acquisition announcement.
The key points presented for Stratix 10 include a claimed 2x performance increase (clocks speed of the core FPGA fabric with “breakthrough power efficiencies”; a 3D integration structure based on Intel’s EMIB (Embedded Multi-die Interconnect Bridge) technology, that permits up to 5.5 million logic elements on a single, monolithic die; quad A53 cores that will clock at up to 1.5 GHz; and FPGA security capabilities via a Secure Device Manager. Altera asserts it has the, “highest performance, highest density FPGA with advanced embedded processing capabilities, GPU-class floating point computation performance and heterogeneous 3D SiP integration”.
Part of the performance gain derives from the “HyperFlex” architecture, which adds large numbers of registers throughout all core interconnect routing segments, enabling the design tools to carry out extensive register retiming, pipelining and other design optimisations. An Altera spokesman describes the resource as “[virtually] unlimited pipelining, for free.” Designers will be able to eliminate critical paths and routing delays, and more-rapidly close timing. Higher core logic performance also enables improvements in device utilisation and power by reducing the need for very wide data paths and other skew-inducing design constructs. Alter estimates the gains as enabling designs to operate with up to 70% lower power by reducing logic area requirements.
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