The cost of ARM’s DS-5 debug tool is $6000 per seat. The cost of the Altera specific version is just $1500.
“This is the first time that ARM has done a vendor specific tool kit,” said Chris Balough, Senior Director of Product Marketing for SoC Products at Altera. "
We have been very aggressive on making sure that no one is left out, with a processor dev kit with a fully featured board where you get all of these tools included."
Altera has started shipping samples of its first SoC FPGA, the largest, which combines two ARM A9 cores with 110,000 logic elements for around $50 to $60.
“We are now beginning to ship the first the largest of the Cyclone class and we have been surprised by how well we have seen market interest and design wins,” said Balough. “Perhaps we wanted to keep our expectations in check but the value proposition for this is where you have an FPGA and processor of a similar calibre, there’s more of that configuration than we realised and there’s a tremendous momentum in the ARM architecture.”
The DS-5 Altera Edition provides access to the two cores and to all the registers in peripheral blocks and embedded memory in the FPGA fabric. The data from across the system is time stamped and correlated in the tool. It supports ARM’s CoreSight debug protocol and SignalTap JTAG protocol so that soft peripheral such as an ARM Cortex M0+ core that are built in the FPGA fabric can also be debugged.
“This is the first silicon IC that implements the new CoreSight global timestamp capability so it is possible to go back as far as you want in the RTL waveforms and instructions with a common timebase,” he said.
“When you have 125Gbit/s bandwidth between the processing subsystem and the FPGA fabric over 4000 wires you can expect people to put memory mapped peripherals out in