Altera’s MAX 10 FPGAs blend programmable logic and analogue

September 30, 2014 // By Graham Prophet
MAX 10 FPGAs host up to 50k logic elements, plus programmable analogue blocks, and retain their configuration in dual-configuration flash memory. By use of a soft-core Nios processor, the can also host embedded processing.

Altera has formally introduced its MAX 10 FPGAs, that it previewed in May 2014 ; they are Altera's latest addition to its Generation 10 family. Using TSMC’s 55 nm embedded flash process technology, they are non-volatile FPGAs with dual-configuration flash,, DSP, analogue and embedded processing capabilities in a small-form-factor, low-cost, instant-on programmable logic device. First chips in the family are available now together with support in a Quartus II software update, evaluation kits, design examples, documentation, training and design services. The products bridge the CPLD and FPGA market sectors, Altera says.

The flash memory is large enough for two complete configuration files, that are loaded into SRAM – the logic is conventional SRAM-based FPGA from Altera’s other ranges – at power-up or on command, in around 10 msec. You can use the twin configurations for alternative functionality, for secure field update or to hold a back-up function set. Altera says it decide not to place a hard processor core on the chips, using instead its Nios II soft core, which is itself configurable to use under 5k logic elements (Les) down to as few as 800 Les; the device family spans 2k to 50k LE capacity. Nios II is “more than adequate” for the processing power required by the type of designs that Altera envisages for the devices, the company says.

Altera positions the chips as reducing overall bill-of-material costs while increasing board reliability. The highly integrated, non-volatile FPGAs provide up to 50% board area savings compared to other low-cost FPGAs by integrating into a single chip:

Up to 50K logic elements

Flash memory blocks (user flash and dual-configuration flash)

Analogue-to-digital converters

Embedded memory and DSP blocks

DDR3 external memory interfaces

Embedded processing with Nios II cores

Up to 500 user I/O

Integrated power regulator

These key features funtion at system-level by enabling MAX 10 FPGAs to perform several important system functions, such as an instant-on configuration, fail-safe upgrades, system