Analog tip; Continuous-time sigma-delta ADCs

August 20, 2015 // By Ian Beavers, Analog Devices
Pipeline ADCs are Nyquist-rate discrete time architectures that will have flat quantisation noise from DC to the Nyquist frequency. Alternate ADC architectures can be implemented for applications not requiring a full Nyquist bandwidth.

Band-Pass continuous time sigma delta (CTΣΔ or CTSD) ADCs use a noise shaping function that essentially ‘pushes’ or filters the in-band quantisation noise outside of the frequency band of interest. In comparison to a discrete time ADC, a CTSD does not use a switched capacitor to sample the input signal.

The noise of a CTSD ADC will be shaped based upon the loop filter response within the modulator. This causes the noise transfer function to have a non-flat shape that is notched considerably lower over a narrow band of interest. It is in this band that the CTSD ADC operates to its maximum performance where the SNRFS is the highest. The AD6676 is a new CTSD IF receiver subsystem with noise spectral density as low as -159 dBFS/Hz across a 20-160 MHz tunable frequency band.

Figure 1. CTSD architectures are based upon loop and decimation filters that shape output noise.

Since one of the main benefits of a CTSD architecture is to detect signals within a narrow frequency band, operation across the wide sampling band is not of particular interest. Instead, the dynamic range within the narrow pass band is what will be highlighted as the performance metric for a CTSD ADC.

Main Highlights:

* Oversampling provides inherent anti-aliasing as harmonics fall out of band beyond the BW of the CTSD. Distortion products would need high frequency components well beyond Fs/2 in order to alias back within the pass-band.

* CTSD architectures use resistive inputs that are easier to drive compared to switched capacitor inputs.

* The requirements for band specific IF anti-aliasing filters can be significantly relaxed due to the pass-band benefits of the internal loop filter, simplifying system architecture.

Some drawbacks:

* A very high frequency clock is needed to achieve an effective oversampling ratio (OSR). For example, a 100 MHz BW CTSD with an OSR of 16 requires a sampling clock of Fs = 2*100 MHz*16 =