The new ARM Approved Design Partner programme also provides DesignStart users with a global list of audited design houses for expert support during development. Via the DesignStart portal, SoC designers can gain free access to ARM Cortex-M0 processor IP for design, simulation and prototyping with the option to buy a simplified and standardized $40,000 fast track licence. The addition of Cadence and Mentor Graphics tools for DesignStart users accelerates the development of custom SoCs for embedded and Internet of Things (IoT) applications. ARM cites costs to fabricate test chips starting at $16,000, using figures from the Europractice multi project wafer pathway, for a batch of 45 samples using 25 mm ² silicon per chip in a 'mature' process at 180nm (not inclusive of EDA tooling and IP licensing costs): the path to custom SoCs is now much easier, ARM contends.
"ARM's DesignStart portal, with its convenient access to the Cortex-M0 package and its low-cost path to commercialization, is already making it easier for start-ups and OEMs to create embedded and mixed-signal SoCs," said Nandan Nayampally, vice president of marketing and strategy, CPU group, ARM. "Simplifying access to EDA tools from Cadence and Mentor Graphics will further spur rapid innovation, creating a fast path to production silicon for companies looking to deliver an embedded or connected IoT product."
The DesignStart portal, which also gives access to a broad range of ARM Artisan physical IP, is available for immediate use at http://designstart.arm.com
The ARM Approved Design Partner program creates a network of design houses that will assist partners designing an SoC for the first time and help in-house teams needing additional support. To be part of the ARM Approved Design Partner program, design houses have to go through a stringent ARM auditing process to ensure they meet the highest quality standards.
Oner such is Sondrel (Reading, UK); "The semiconductor industry has high expectations for future growth in the