The new agreement also extends a long-standing collaboration to include graphics processors. As part of the agreement, ARM will develop a full platform of ARM Artisan Physical IP, including standard cell libraries, memory compilers and POP IP solutions. The results will help enable a new level of system performance and power-efficiency for a range of mobile applications, from smartphones to tablets to ultra-thin notebooks.
The companies have been collaborating for several years to jointly optimize ARM Cortex-A series processors, including multiple demonstrations of performance and power-efficiency benefits on 28nm as well as a 20nm test-chip implementation currently running through GlobalFoundries' fab in Malta, New York state. This agreement extends the prior efforts by driving production IP platforms that will enable customer designs on 20nm and promote rapid migration to three-dimensional FinFET transistor technology.
GlobalFoundries plans to develop optimized implementations and benchmark analysis for next-generation, energy-efficient ARM Cortex processor and Mali graphics processor technologies, building on the existing Artisan physical IP platforms for 65nm, 55nm, and 28nm technology, as well as the Cortex-A9 POP technology for 28nm SLP. FinFET will follow the 20nm implementation.
“This early engagement promotes the rapid adoption of ARM and GlobalFoundries technologies in future SoCs for several important markets,” said Simon Segars, executive vice president and general manager, Processor and Physical IP Divisions at ARM. “Customers designing for mobile, tablet and computing applications will benefit extensively from the energy-efficient ARM processor and graphics processor included in this collaboration. By proactively working together to enable next-generation 20nm-LPM and FinFET process technologies, our mutual customers can be assured a range of implementation options that will enable two more generations of advanced semiconductor devices.”
The POP IP products have three critical elements, from Artisan physical IP standard cell libraries and memory cache instances that are specifically tuned for a given ARM processor and foundry technology to benchmarking for the processor implementation across an envelope of configuration and design targets and