ARM reveals Cortex A-15 dual core hard macro, power-optimised in 28nm technology

May 28, 2013 // By Nick Flaherty
ARM has launched a 28nm dual-core hard macro implementation of its Cortex-A15 processor to further reduce the power consumption in mobile chip designs.

The ARM Cortex-A15 implementation provides exceptional power efficiency and is capable of delivering up to 10,000 DMIPS within a constrained mobile power envelope and can be used as part of a big.LITTLE processing sub-system.
The ARM Cortex-A15 hard macro development is the result of combining the Cortex processor IP, Artisan physical IP, CoreLink systems IP and ARM’s integration capabilities, and uses TSMC’s 28nm HPM process.
The complete low-leakage implementation features integrated NEON SIMD technology and a virtual floating point engine, and includes a 1MB level 2 cache for a wide range of power-sensitive handheld devices such as mobile phones and tablets. It uses ARM Artisan 9-track libraries and incorporates ARM POP Technology for the Cortex-A15.
This Cortex-A15 implementation is a solution for designers of big.LITTLE processing systems as it can be paired with a dual- or quad-core Cortex-A7 processor, simplifying the design process and enabling a faster time to market.
This hard macro is suitable for designers looking for a cost-effective, highly power-efficient Cortex-A15 dual-core solution for mobile applications, and also devices such as single board computers that are used across a wide array of end-markets.