The execution pipeline has been reduced to two stages from three in the previous M0 core, splitting the instruction decode between the fetch and execution units. This has provided more responsiveness for cycle intensive operations and branches, as wel as reducing energy loss through unused branches as only one instruction is lost.
The move to a two stage pipeline hasbeen possible with the improvements ot the process technology so that more functions can be handled within the cycle time as the frequency remains around 50MHz. More gates are available and these have been used for power gating in the core to reduce the power of sections that are not in use. The result is power consumption of 9µA/MHz on a low-cost 90nm LP process, around one third of the energy of any 8- or 16-bit processor available today with the same 12,000 gates as the preious M0 core.
The memory interface has also be optimised, allowing two 16bit transfers in a cycle so that the on-chip flash memory can be accessed half the time.
The core still uses the same 16bit Thumb-2 instruction set as the M0, making it upwards compatible with the M3 and M4 families. The compiler handles M0, M3 and M4 code all together for ease of use and there are options to include debug and trace hardware alongside the core.
The Cortex-M0+ processor features enable the creation of smart, low-power, microcontrollers to provide efficient communication, management and maintenance across the 'Internet of Things’, which is a specific target for ARM.
“The Internet of Things will change the world as we know it, improving energy efficiency, safety, and convenience,” said Tom Halfhill, a senior analyst with The Linley Group and senior editor of Microprocessor Report. “Ubiquitous network connectivity is useful for almost everything - from adaptive room lighting and online video gaming to smart sensors and motor control. But it requires extremely low-cost, low-power processors that still