ARM updates CoreLink for next-gen heterogeneous SoCs

October 28, 2015 // By Graham Prophet
ARM’s CoreLink system IP has been designed to enhance system performance and efficiency in next-generation premium mobile devices. The CoreLink CCI-550 interconnect enables ARM big.LITTLE processing and a fully coherent GPU while lowering latency and increasing peak throughput.

The associated CoreLink DMC-500 memory controller provides higher bandwidth and latency response for processors and display. Both CoreLink products have been delivered to lead partners and are available for licensing with production silicon expected by late 2016. “An optimised path to memory is essential for a best-in-class SoC that addresses the demanding mobile market,” said Monika Biddulph, general manager, systems and software group, ARM.

The improved support for GPU coherency in CoreLink CCI-550 enhances power management and delivers system-wide advantages. Coherency reduces development costs and time for new applications accelerated by heterogeneous processing for more efficient utilisation of compute engines. OpenCL 2.0 with shared virtual memory features and other newer programming models take full advantage of system coherency. All processors work on the same data without unnecessary cache maintenance or memory copying. This also enables a system architecture fully aligned with the HSA (Heterogeneous System Architecture) coherency standards.

CoreLink CCI-550 includes improvements in the microarchitecture to deliver higher peak throughput for demanding use cases and quality of service (QoS) enhancements that reduce latency by 20%. SoC designers can configure the number of memory channels, tracker sizes, snoop filter capacity and scale up to six fully coherent processor clusters. The increased scalability addresses a wide range of applications beyond mobile including digital TV, automotive and cost-efficient networking applications.

Time and energy-intensive memory transactions require a memory controller designed with a system approach to reduce bottlenecks. For ARM Cortex processors, CoreLink DMC-500 offers the lowest latency and power along with enhanced QoS for LPDDR4/3 memories operating up to LPDDR4-4267 transfer speeds. When integrated at the design level, CoreLink CCI-550 and CoreLink DMC-500 work together to deliver a peak system memory bandwidth beyond 50 GB/sec for access to richer content such as 4K video, with predictable performance, leading to the best user experience in premium smartphones and tablets.

ARM; www.arm.com