Asynchronous SRAMs with on-chip ECC boost data integrity

September 05, 2014 // By Graham Prophet
Cypress Semiconductor has announced that it is sampling 16 Mbit asynchronous low-power SRAMs with Error-Correcting Code (ECC). In the low-power MoBL family of devices, Cypress says that these parts improve data reliability by a factor of one thousandfold over SRAMs without ECC, while helping to conserve battery life.

The on-chip ECC feature of the new MoBL (More Battery Life) SRAMs enables them to provide the highest levels of data reliability, without the need for additional error correction chips—simplifying designs and reducing board space. The MoBL devices extend the battery life of handheld systems for a wide variety of markets, including industrial, military, communication, data processing, medical and consumer electronics.

Soft errors caused by background radiation can corrupt memory content, resulting in a loss of critical data. A hardware ECC block in Cypress's new asynchronous SRAM family performs all error correction functions inline, without user intervention, delivering Soft Error Rate (SER) performance of less than 0.1 FIT/Mbit (one FIT is equivalent to one error per billion hours of device operation). The new devices are pin-compatible with current asynchronous low-power SRAMs, enabling designers to boost system reliability while retaining board layout. The 16 Mb MoBL SRAMs also include an optional error indication signal that indicates the occurrence and correction of single-bit errors.

The 16-Mbit MoBL SRAMs come in industry standard x8, x16 and x32 configurations. The devices operate at multiple voltages (1.8V, 3V, and 5V) over -40C to +85C (Industrial) and -40C to +125C (Automotive-E) temperature ranges. They are sampling in industrial temperature grade, with production expected in November 2014. These devices will be available in RoHS-compliant 48-pin TSOP I, 48-ball VFBGA and 119-ball BGA packages.

Cypress; www.cypress.com