MiP is specially designed for smart card makers seeking to implement biometrics and other strong user authentication in smart cards, secure microcontrollers, tokens and mobile devices.
During an authentication process, the direct bit-to-bit comparison of the stored reference pattern to be authenticated occurs within the memory array. This is unlike traditional methods where often the secret keys stored in other memory types need to be downloaded from the memory and cached in a register where switching operations could be analysed. In the new MiP approach, the sensitive data stored in a Magnetic Logic Unit (MLU) array is never revealed to an external bus or register. This makes the security more robust. It takes MiP less than 70nsec to perform a user authentication match. Therefore, the window of opportunity to carry out a security attack is significantly reduced or virtually non-existent. The MiP prototype has a maximum of 32-bits of MiP to demonstrate a 4 – 10 digit PIN code match. Crocus will make MiP available as a FPGA (Field Programmable Gate Array) demonstrator in Q3 2013.
Each cell of the MiP technology is a non-volatile memory cell combined with the virtual XOR gate (digital logic gate) of the MLU. Multiple cells are connected in series to a NAND chain acting as a linear MiP engine. In digital electronics, a NAND gate (Negated AND) is used to accomplish bit-to-bit comparisons. If multiple MiP NAND chains are placed in parallel, they can act simultaneously to compare one pattern against many. A Match in Place white paper is available for review: http://www.crocus-technology.com/papers.html
Crocus Technology; www.crocus-technology.com