The compiler is said to be the first timing-driven, multi-FPGA partitioning software for ASIC and SoC prototyping. According to the EDA vendor, the tool typically delivers a 10X clock frequency increase, runs blazingly fast, handles multi-billion ASIC gates equivalents designs, and maps them to any Altera or Xilinx board, whether it's off-the-shelf or custom.
Wasga Compiler automatically partitions large designs onto multiple FPGAs while addressing chip resources, connectivity, and the clock frequency constraints required for running software applications in near real time. It maximizes prototyping system performance and solves hardware/software validation bottlenecks of next generation SoCs to help meet the time-to-market challenges.
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