Avago demonstrates 56Gbps PAM4 SerDes

January 16, 2015 // By Graham Prophet
Avago reports that its customers are designing in Avago PAM4 transceivers across copper backplane, direct-attached cables and optics, doubling system I/O bandwidth

Avago says that this is the industry’s first 56Gbps pulse-amplitude modulation (PAM)4 SerDes transmission across copper backplanes and optical interconnects targeting next-generation switches and routers. Leading OEM customers are presently designing advanced ASIC SoC solutions in 28nm and 16FF+ process technologies using the Avago PAM4 SerDes cores.

PAM4 technology enables future scaling of core/metro router and hyperscale data centres by more than doubling link full-duplex throughput to 56 Gbps from 25 Gbps per SerDes lane. Rack-level applications will particularly benefit from PAM4 technology realising advantages in space, power, cost, and simplified cabling.

The Avago 56Gbps PAM4 SerDes is designed to support a wide range of copper and optical interconnects ranging from chip-to-chip, chip-to-module, low- cost direct-attached cable, and copper backplane down to 35 dB loss. The SerDes supports speeds from 1 Gbps to 56 Gbps, including existing 10G/25G/40G/50G/100G Ethernet, Fibre Channel, and OIF CEI NRZ speeds, providing investment protection and a forward-looking architecture path to networking, compute system vendors, and mega data centre companies.

By also targeting emerging OIF CEI-56G-VSR and IEEE 802.3bs (400GE) electrical standards defining next generation chip-to-module interconnect, the Avago 56Gbps PAM4 SerDes provides the additional benefit of enabling the same PAM4 signalling deployment on front side and back side interfaces, thus increasing SoC use case flexibility and reusability across hardware platforms.

The Avago 56Gbps PAM4 SerDes, now available in silicon, is running PRBS31 traffic, error-free, across various interconnects up to 56 Gbps, thus reducing ASIC development risk and accelerating system deployment.

Avago Technologies; www.avagotech.com