BER tests promise faster design verification of high-speed digital systems

January 22, 2014 // By Graham Prophet
Offering improved insight into performance margins of high-speed digital devices, Agilent’s M8000 Series BER test solution is an integrated and scalable bit error ratio test solution for physical-layer characterisation, validation and compliance testing for receivers used in multigigabit digital designs.

With support for a wide range of data rates and standards, the M8000 Series addresses problems faced by R&D and validation teams characterising next-generation designs; the faster data rates of the emerging next-generation digital computer buses, such as PCI Express 4 (with a bit rate of 16 GT/sec) and USB 3.1 (with a bit rate of 10 Gb/sec), present new signal integrity test challenges. New 128/130-bit and 128/132-bit coding formats complicate error detection and loopback pattern creation. Widespread adoption of mobile computing devices means more R&D and test engineers need to test different implementations of MIPI ports, with new data formats, termination models, multiple lanes and built-in error counting.

With the enormous surge in data-centre traffic, servers and storage designs must support much higher bandwidths on their backplane and networking ports. Data rates of 25 Gb/sec and more on multiple lanes over PC boards, cable or optical interconnects are required by most of the latest industry standards, such as 100GbE, CEI and Fibre Channel. Testing such 25-Gb/sec receiver ports requires new test capabilities to characterise device tolerance for interference, channel losses and crosstalk.


The first model in the new M8000 Series is the J-BERT M8020A high-performance BERT. It enables fast and accurate receiver characterisation of single- and multilane devices operating at data rates up to 16 Gb/sec and 32 Gb/sec. The M8020A accelerates insight into designs by:

- Streamlining receiver test setup by providing the highest level of integration. It offers built-in jitter injection, 8-tap de-emphasis, interference sources, reference clock multiplication, clock recovery and equalisation.

- Ensuring accurate and repeatable measurements by automating in-situ calibration of signal conditions.

- Reducing the effort required to bring devices into loopback test mode because the M8020A behaves like a link partner for the device under test and supports interactive link training for PCIe devices.

The J-BERT M8020A high-performance BERT is scalable and expandable to meet future test needs. It supports one to