The updated platform includes new technologies within the Cadence Virtuoso Analog Design Environment (ADE) and enhancements to the Cadence Virtuoso Layout Suite to address requirements for automotive safety, medical device and IoT applications.
The next-generation Cadence Virtuoso ADE product suite addresses the challenges that come with the emergence of new industry standards, advanced-node designs and the requirements for system design, enabling engineers to fully explore, analyze and verify designs to ensure that design intent is maintained throughout the design cycle. Enhanced data handling provides up to 20X improvement in waveform loading and a 50X improvement in versioning and loading set-up files with databases in excess of 1GB. The suite’s key technologies include:
Virtuoso ADE Explorer which allows fast and accurate real-time tuning of design specs, provides pass/fail datasheets and delivers a complete corners and Monte Carlo statistical environment for detecting and fixing variation problems.
Virtuoso ADE Assembler which enables engineers to analyze their designs under various process-voltage-temperature (PVT) combinations; also offers GUI-based verification plans so designers can easily create conditional and dependent simulations.
Virtuoso ADE Verifier which provides a substantial technological advancement in analog verification, offering an integrated dashboard that lets engineers easily verify that all of the blocks are contributing to the overall design specifications.
And Virtuoso Layout Suite enhancements that address the most complex layout challenges by offering accelerated performance and productivity for custom analog, digital and mixed-signal designs at the device, cell, block and chip levels. The suite’s features improved graphics rendering, offering from 10X to 100X accelerated zoom, pan, drag and draw performance on large layouts. An interactive pattern manipulation flow makes real-time customization of the Module Generator very visual and simple; it now supports synchronous clones, which are layout elements with identical physical properties—like width and length of transistors—that the layout designer can layout once and reuse. The new Pin-to-trunk routing capabilities can enhance routing productivity by as much as 50 percent.
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