Cadence adds in-circuit acceleration to its system development suite

May 16, 2012 // By Julien Happich
Cadence Design Systems announced a new in-circuit acceleration based on its Incisive and Palladium XP platforms.

The effort and cost associated with using different, disconnected engines for virtual prototyping, RTL simulation, acceleration, emulation, and FPGA-based prototyping pose key challenges to delivering products on time. Cadence now offers a single heterogeneous environment for system-level verification, which enables designers to leverage both the high speed and real-world interfaces of traditional in-circuit emulation environments combined with the advanced analysis capabilities available in RTL simulation. Design teams are no longer forced to create and maintain both environments, spend unnecessary time and effort to reproduce bugs, or remodel all system components targeted for one environment – tasks which are not time effective and make sub-optimal use of the existing IP assets.

New in-circuit acceleration enables teams for simulation acceleration and emulation to deploy a common unified verification environment, resulting in up-to-10x increased efficiency during system-level validation and root cause analysis, according to the EDA vendor. It further shortens system and SoC development times by delivering an optimal blend of performance and accuracy and optimal leverage of existing IP assets. Universal Verification Model (UVM)-compatible accelerated verification IP (VIP) enables users to smoothly transition from simulation to acceleration, in-circuit acceleration, and in-circuit emulation, giving them the ability to verify complex Systems and SoCs that are simply too large for effective verification using traditional RTL simulation. The Cadence VIP catalog now includes Accelerated VIP for the following interface standards: ARM’s AMBA AXI 3/4 and ACE, PCI Express 2.0/3.0, USB 3.0, 10Gb Ethernet, SATA 3, and HDMI 1.4.

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