Cadence adds to IP offering for analogue in 28-nm, and in Tensilica audio blocks

October 11, 2013 // By Graham Prophet
Cadence Design Systems has recently been expanding its profile in IP (intellectual property) for SoC chip design and has added to its offering with three separate announcements in recent days.

The company's Christian Malter, director of technology solutions and business development in the EMEA region, noted the growing importance of the IP offering and the company acquisitions that Cadence has made: he comments, “Ten years ago IP was not profitable – now it is.” Malter was introducing new IP including high-performance data coverters for 28-nm silicon processes; audio DSP for the Dolby Digital Plus audio stream; and, also in the audio space, an IP core for DTS Neural Surround.

The converter technology comprise two ADCs and two DACs that are ten-times faster than any other competing IP, Cadence claims. These analogue designs are intended for next-generation high-speed wired and wireless communications applications, such as WiGig (802.11ad), which runs on a 60 GHz spectrum with potential data throughput up to 7 Gbps, as well as LTE and LTE Advanced.

The data converter family includes: 7-bit 3 GSPS dual ADC and DAC; 11-bit 1.5 GSPS dual ADC; and a 12-bit 2 GSPS dual DAC. The data converter IP cores combine to form a complete analogue front end (AFE) IP solution for wired/wireless communications, infrastructure, imaging and software-defined radios.

The ADC IP cores are developed with a parallel Successive Approximation Array (SAR) architecture, producing extremely fast and scalable sample rates. High Effective-Number-of-Bits (ENOB) values are achieved with a unique implementation and built-in background auto calibration, producing more accurate conversion and consistent performance. The Cadence IP includes features such as differential data inputs, reference and timing generator, internal offset correction, and voltage regulators for improved supply noise immunity.

The DAC IP cores use a current switching architecture and include a digital multiplexer and FIFO for easy integration into an SoC. The DACs include digital gain control and all required reference circuitry.

All the IP includes multi-level power-down modes for additional power savings, a built-in analogue test bus for design testability, and single-ended CMOS or differential Current-Mode Logic (CML) clock inputs for a flexible clock