Cadence adds targeted tool link for IC power sign-off

November 13, 2013 // By Graham Prophet
Cadence has introduced a power integrity analysis engine with massively parallel execution that brings up to 10X faster performance; its hierarchical architecture supports very large designs up to 1 billion instances; and it is integrated with key Cadence tools throughout the design flow, including Cadence Tempus Timing Sign-off Solution.

Addressing critical power challenges, the Voltus IC Power Integrity Solution, Cadence says, enables design teams to better manage power issues throughout the product development cycle and achieve faster design closure.

Following the earlier release of Tempus Timing Signoff, the Voltus solution aims at further speeding design sign-off and closure. Using the Voltus solution, Cadence customers can shrink the critical power signoff closure and analysis phase to a minimum through its massively distributed parallel power integrity analysis engine, hierarchical architecture that scales to multiple CPU cores and servers, and SPICE-accurate solver technology that provides the most accurate power signoff results. Voltus has physically-aware power integrity optimisation, such as early rail analysis, de-coupling cap and power gating switches, that improves physical implementation quality and speeds up design closure.