In addition to increased chip performance, Netronome engineers using the latest Encounter 11.1 technology achieved a 29% reduction in power consumption, smaller design area and faster overall time to market compared to their former flow, for SoCs targeting the secure virtualized cloud and data center markets. The Cadence En counter RTL-to-GDSII flow - including RTL Compiler, the Encounter Digital Implementation System, and Encounter Test - helps design teams optimize power, performance, and area for the world's most advanced high-performance, low-power SoC designs.
Netronome's OEM customers have constraints on power budgets, which required the company to optimize its high-performance 40Gbps NFPs for low-power consumption for use in their customers' switches, routers, load balancers and cyber-security platforms. Netronome engineers were tasked with improving chip power efficiencies across multi-mode, multi-corner and on-chip variation scenarios. Implementing robust clock trees that consume less dynamic switching and static leakage power without compromising on performance was difficult under such extreme requirements. Furthermore, as chip power consumption increases, it costs more to design, fabricate, operate and cool devices and systems.
“Using the complete Cadence Encounter RTL-to-GDSII flow, we were able to tape out a complex 1.4 GHz 40-core micro-engine-based Network Flow Processor on schedule, achieving a 29 percent power savings and 10 percent improvement in timing,” said Jim Finnegan, senior vice president, Silicon Engineering at Netronome. “We were particularly impressed with the newly integrated Clock Concurrent Optimization ( CCOpt ) technology in the Encounter flow and its unique ability to optimize clocks and data-path simultaneously allowing us to eliminate several manual design steps and achieve superior performance, power and area results on our design. This gives us a competitive advantage in our end market.”
Clocks are the backbone of all digital chips, and a fundamentally different approach to clock construction and optimization was needed. Traditional clock tree synthesis (CTS) tools and methodologies - which are based on minimizing skew and are isolated from logic/physical optimization -