Cadence has IP, tools for 16-nm FinFET Plus node; looks onwards to 10nm

September 30, 2014 // By Graham Prophet
Cadence Design Systems has today announced a portfolio of intellectual property (IP) for TSMC’s 16nm FinFET Plus (16FF+) process. The IP for the 16FF+ process enables systems and semiconductor companies to take advantage of the 15% speed improvement with same total power or 30% total power reduction at the same speed compared to the16FF process.

Currently under development for the 16 FF+ process, the Cadence IP portfolio includes multiple high-speed protocols for several key memory, storage and interconnect standards critical in the development of advanced SoC designs. Silicon-tested IP is expected to be available beginning in Q4 2014.

Cadence also announced the qualification of its digital implementation, signoff and custom/analogue design tools for the 16nm FinFET Plus process. Its digital and custom/analogue tools have achieved V0.9 Design Rule Manual (DRM) and SPICE certification from TSMC for its 16FF+ process: 16FF+ V1.0 certification is on track to be concluded by November 2014. Cadence also collaborated with TSMC to make several enhancements to its Custom Design Reference Flow (CDRF) for the 16FF+ process. Additionally, Cadence and TSMC are collaborating on the 10nm FinFET process, and Cadence says solutions are ready to support 10nm early customer design starts.

The Cadence custom/analogue and digital implementation and signoff tools have been validated by TSMC on high-performance reference designs in order to provide customers with the fastest path to design closure. Cadence tools certified for 16FF+ include Encounter Digital Implementation System, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Quantus QRC Extraction Solution, Virtuoso custom design platform, Spectre simulation platform, Physical Verification System, Litho Physical Analyzer and CMP Predictor.

Enhancements to the CDRF include an exclusive TSMC application programming interface (API) incorporated into Virtuoso Analog Design Environment GXL that speeds up statistical simulation flow, a new design methodology usung module generator (ModGen) technology for designing FinFET arrays to avoid density gradient effects, and the introduction of the electrically-aware design (EAD) platform to extract and analyse real-time parasitics and electromigration (EM) violations during design implementation. Cadence tools in the flow include Virtuoso custom design platform, Integrated Physical Verification System, Physical Verification System, Quantus QRC Extraction Solution, Spectre simulation platform, Voltus-Fi Custom Power Integrity Solution and Litho Electrical Analyser.

According to Dr. Chi-Ping Hsu, senior vice president, chief strategy officer, EDA and